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Verification

Area of expertise that are dealing with simulation, validation and verification of ICs.

Dynamic Virtual Analyzer and Simulator

Tool Name (abbreviation): 
D-VASim
Author(s): 
Hasan Baig, DTU C...
(unregistered) Author(s): 
Madsen, Jan
Screenshot: 

D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).

Project Information
Project Acronym: 
D-VASim
Project Start: 
Fri, 08/15/2014
Project End: 
Fri, 03/11/2016
Tag your tool
Keywords: 
D-VASim
Genetic logic circuits
SBML
Systems biology
synthetic biology
genetic circuits
stochastic simulation
deterministic simulation
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analysis
Biological Information Sensing System
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computation
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D-VASim
deterministic simulation
genetic circuits
Genetic logic circuits
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run-time
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Simulation-Based Verification
software verification
stochastic simulation
synthetic biology
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