D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).
eTeak is a high-level synthesis EDA, that aims to generate Globally Asynchronous Locally Synchronous (GALS) SoCs from a timing-free description. eTeak is a synchronous extension to the Teak Synthesis system which is a dataflow backend for the Balsa language. eTeak adopts Synchronous Elastic Protocol to provide a common timing behaviour in the computation and communication domains. This work is a part of The GAELS project supported by EPSRC under research grant EP/I038306/1.
GAUT is an open source High-Level Synthesis tool. From a bit-accurate C/C++ specification it automatically generates a pipelined RTL architecture described in VHDL and SystemC simulation models (TLM and CABA).
Technology porting of circuit schematics between two process nodes with powerful parameter conversion and automatic wiring of the new symbols
Converting schematics from several formats (e.g. PSpice) into Cadence schematics
Generating PDF documents with hierarchically linked cells from circuit designs of commercial systems (such as Cadence ®)
Export of vector graphics (eg SVG, EMF) for use in Office documents and presentations
Graphical user interface to display and modify schematics
Runs on all operating systems supporting Java 1.6 and higher
