D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).
eTeak is a high-level synthesis EDA, that aims to generate Globally Asynchronous Locally Synchronous (GALS) SoCs from a timing-free description. eTeak is a synchronous extension to the Teak Synthesis system which is a dataflow backend for the Balsa language. eTeak adopts Synchronous Elastic Protocol to provide a common timing behaviour in the computation and communication domains. This work is a part of The GAELS project supported by EPSRC under research grant EP/I038306/1.
