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Dynamic Virtual Analyzer and Simulator

Fri, 03/11/2016 - 12:05 — Hasan Baig, DTU C...
Tool Name (abbreviation): 
D-VASim
Author(s): 
Hasan Baig, DTU C...
(unregistered) Author(s): 
Madsen, Jan
Screenshot: 
Download URL: 
Download D-VASim for MAC and Windows OS
Homepage: 
Bio Design Automation at Technical University of Denmark

D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).

Project Information
Project Acronym: 
D-VASim
Project Homepage: 
D-VASim
Project Start: 
Fri, 08/15/2014
Project End: 
Fri, 03/11/2016
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Keywords: 
D-VASim
Genetic logic circuits
SBML
Systems biology
synthetic biology
genetic circuits
stochastic simulation
deterministic simulation
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Prototype
DATE
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Design Automation Methodology
Concept Engineering
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Functional Verification
Simulation
Test Verification
Accuracy Evaluation
analysis
Biological Information Sensing System
CAD
CAD Tool
computation
Computer aided design
D-VASim
deterministic simulation
genetic circuits
Genetic logic circuits
Graphic User Interface (GUI)
run-time
SBML
Simulation-Based Verification
software verification
stochastic simulation
synthetic biology
Demonstration
Development
Released
Knowledge and Education
Training
Research Institute

A Data-driven Synchronous Elastic Synthesiser

Mon, 01/18/2016 - 12:27 — Mahdi Jelodari Ma...
Tool Name (abbreviation): 
eTeak
Author(s): 
Mahdi Jelodari Ma...
Download URL: 
eTeak on Github
Homepage: 
eTeak @ Advanced Processor Technologies Group

eTeak is a high-level synthesis EDA, that aims to generate Globally Asynchronous Locally Synchronous (GALS) SoCs from a timing-free description. eTeak is a synchronous extension to the Teak Synthesis system which is a dataflow backend for the Balsa language. eTeak adopts Synchronous Elastic Protocol to provide a common timing behaviour in the computation and communication domains. This work is a part of The GAELS project supported by EPSRC under research grant EP/I038306/1.

Project Information
Project Acronym: 
GAELS
Project Start: 
Sat, 01/01/2011
Project End: 
Thu, 12/31/2015
Project Funding ID: 
EPSRC - The University of Manchester (PhD Scholarship)
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Abstraction Level of Electronic Systems
Architecture Design
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ASPDAC
DAC
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Design Automation Methodology
Specification
Implementation
Synthesis
CAD
CAD Tool
EDA
FPGAs
High-Level Synthesis
Low Power

EDADB - Tools for semi-automatic Technology Porting of Integrated Mixed-Signal Circuits and Documentation

Mon, 09/10/2012 - 15:47 — Volker Boos, Inst...
Tool Name (abbreviation): 
EDADB
Author(s): 
Volker Boos, Inst...
Screenshot: 
Homepage: 
http://www.tu-ilmenau.de/imms_topo

Technology porting of circuit schematics between two process nodes with powerful parameter conversion and automatic wiring of the new symbols
Converting schematics from several formats (e.g. PSpice) into Cadence schematics
Generating PDF documents with hierarchically linked cells from circuit designs of commercial systems (such as Cadence ®)
Export of vector graphics (eg SVG, EMF) for use in Office documents and presentations
Graphical user interface to display and modify schematics
Runs on all operating systems supporting Java 1.6 and higher

Project Information
Project Acronym: 
SyEnA
Project Homepage: 
Syntheseunterstützter Entwurf analoger Schaltungen
Project Start: 
Wed, 10/01/2008
Project End: 
Fri, 09/30/2011
Project Funding ID: 
01 M 30 86
Project Description: 
Within the framework of the SyEnA project new automatable methods for analog circuit design are being developed for the first time; these include the whole design chain from the specification to the production plan. These methods are leading to a significant increase in quality and productivity as well as providing new opportunities for developing innovative complex systems. This paves the way for new types of products especially in the areas where safety is critical – in medical technology and automobile electronic.
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Keywords: 
analog circuit
Synthesis
Categorize your Tool: 
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Analog Mixed Signal
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Design Automation Methodology
Propriety SW
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CAD Tool
design automation
design methodology
design methods
Germany
IKT2020
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