D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).
C++TESK Testing ToolKit is an open-source C++ based toolkit intended for automated functional testing of software components (mostly in C/C++) and RTL (HDL) models of digital hardware (in Verilog and VHDL). The main part of the toolkit is a library of C++ classes and macros that define facilities for constructing formal specifications (reference models), adapters of components under test, test scenarios and test coverage metrics. Basing on C++ descriptions provided by a user, a test system is compiled.
Technology porting of circuit schematics between two process nodes with powerful parameter conversion and automatic wiring of the new symbols
Converting schematics from several formats (e.g. PSpice) into Cadence schematics
Generating PDF documents with hierarchically linked cells from circuit designs of commercial systems (such as Cadence ®)
Export of vector graphics (eg SVG, EMF) for use in Office documents and presentations
Graphical user interface to display and modify schematics
Runs on all operating systems supporting Java 1.6 and higher
