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Dynamic Virtual Analyzer and Simulator

Fri, 03/11/2016 - 12:05 — Hasan Baig, DTU C...
Tool Name (abbreviation): 
D-VASim
Author(s): 
Hasan Baig, DTU C...
(unregistered) Author(s): 
Madsen, Jan
Screenshot: 
Download URL: 
Download D-VASim for MAC and Windows OS
Homepage: 
Bio Design Automation at Technical University of Denmark

D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).

Project Information
Project Acronym: 
D-VASim
Project Homepage: 
D-VASim
Project Start: 
Fri, 08/15/2014
Project End: 
Fri, 03/11/2016
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Keywords: 
D-VASim
Genetic logic circuits
SBML
Systems biology
synthetic biology
genetic circuits
stochastic simulation
deterministic simulation
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Prototype
DATE
University Booth
Design Automation Methodology
Concept Engineering
Test Specification
Prototyping
Verification
Functional Verification
Simulation
Test Verification
Accuracy Evaluation
analysis
Biological Information Sensing System
CAD
CAD Tool
computation
Computer aided design
D-VASim
deterministic simulation
genetic circuits
Genetic logic circuits
Graphic User Interface (GUI)
run-time
SBML
Simulation-Based Verification
software verification
stochastic simulation
synthetic biology
Demonstration
Development
Released
Knowledge and Education
Training
Research Institute

GAUT: High-Level Synthesis Tool (from C/C++ to RTL)

Mon, 09/24/2012 - 17:06 — Philippe Coussy, ...
Tool Name (abbreviation): 
GAUT
Author(s): 
Philippe Coussy, ...
(unregistered) Author(s): 
Dominique Heller
Dr. Pierre Bomel (pierre.bomel@univ-ubs.fr)
Download: 
application/pdf icongaut-date-ubooth-2010.pdf
Download URL: 
http://www.gaut.fr/
Homepage: 
http://www.gaut.fr/

 GAUT is an open source High-Level Synthesis tool. From a bit-accurate C/C++ specification it automatically generates a pipelined RTL architecture described in VHDL and SystemC simulation models (TLM and CABA).

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Keywords: 
High-Level Synthesis; ESL; EDA; FPGA; ASIC; SoC; hardware design; RTL; SystemC; TLM; DSE; CAD; GCC
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Prototype
Design Automation Methodology
Synthesis

EDADB - Tools for semi-automatic Technology Porting of Integrated Mixed-Signal Circuits and Documentation

Mon, 09/10/2012 - 15:47 — Volker Boos, Inst...
Tool Name (abbreviation): 
EDADB
Author(s): 
Volker Boos, Inst...
Screenshot: 
Homepage: 
http://www.tu-ilmenau.de/imms_topo

Technology porting of circuit schematics between two process nodes with powerful parameter conversion and automatic wiring of the new symbols
Converting schematics from several formats (e.g. PSpice) into Cadence schematics
Generating PDF documents with hierarchically linked cells from circuit designs of commercial systems (such as Cadence ®)
Export of vector graphics (eg SVG, EMF) for use in Office documents and presentations
Graphical user interface to display and modify schematics
Runs on all operating systems supporting Java 1.6 and higher

Project Information
Project Acronym: 
SyEnA
Project Homepage: 
Syntheseunterstützter Entwurf analoger Schaltungen
Project Start: 
Wed, 10/01/2008
Project End: 
Fri, 09/30/2011
Project Funding ID: 
01 M 30 86
Project Description: 
Within the framework of the SyEnA project new automatable methods for analog circuit design are being developed for the first time; these include the whole design chain from the specification to the production plan. These methods are leading to a significant increase in quality and productivity as well as providing new opportunities for developing innovative complex systems. This paves the way for new types of products especially in the areas where safety is critical – in medical technology and automobile electronic.
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Keywords: 
analog circuit
Synthesis
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Prototype
Analog Mixed Signal
DATE
Design Automation Methodology
Propriety SW
SW Business Model
CAD Tool
design automation
design methodology
design methods
Germany
IKT2020
Research Institute
Design Group
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