The Redefis system is an SoC design platform for high level, fast implementation of ASIPs 1.The platform is composed of a reconfigurable instruction-set processor and a set of design tools. The developed processors can be used as flexible co-processors in a MPSoC 2 systems or as standalone processor/engines.

Projects:
Refidis

Contact:
Victor GOULART (redefis@fleets.jp)