System On Chip LIBrary: Open Modelling & Simulation Platform for System on Chip Design : The core of the platform is a library of simulation models for virtual components (IP cores), with a guaranteed path to silicon. All simulation models will be distributed as open source and available to all academic institution or industrial company. A synthesizable RTL model must exist for each SoCLib component, in order to guaranty a path to silicon for any system designed with the SoCLib library. The RTL synthesizable models are NOT part of the SoCLib library, in order to preserve the IP providers business. Research topics associated to SOCLIB : * Simulation acceleration for cycle accurate SoCLib models * Formal proof of equivalence between models : RTL model / CABA model / TLM model. * Use of the simulation models as input for hardware synthesis. * Tools for automatic generation and configuration of embedded micro-networks (NoC).