SystemC Studio provides an interface between RT level VHDL/Verilog descriptions and high level descriptions in SystemC and SystemC TLM. This environment facilitates post-synthesis SystemC TLM descriptions to be simulated along with existing RTL VHDL or Verilog designs. This is done by translating VHDL/Verilog codes into RT level SystemC, linking them with post-synthesis SystemC codes coming from synthesis of high level TLM descriptions, and generating a SystemC/C++ model of the entire hardware to be simulated and verified. This environment also provides SystemC translation to VHDL for RTL synthesis of post high-level synthesis TLM descriptions.

Contact:
Homa Alemzadeh (m.sedghi@ece.ut.ac.ir)