This demo presents a design suite that enhances the classical design flow for embedded systems to introduce reliability-awareness. The methodological approach adopted in the tools is based on a design space exploration to optimize the hardening of the final system by selectively applying reliability-oriented techniques for autonomous management of fault occurrence. The suite is composed by a set of design tools focusing on two specific steps of the design flow: the system-level synthesis on heterogeneous multiprocessor systems and the design of hardened hardware accelerators on FPGA devices.