Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. The presence of process variations further deteriorates these problems. In this demonstration, we will present statistical techniques to evaluate the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, we will provide a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40 degree Celsius hotter and 23% leakier than its 2D counterpart and (3) the proposed tierstacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.