In this demonstration, we will show a redundant via (RV) insertion tool that integrates router design, cell library engineering, and post-routing RV insertion. Our tool is designed particularly to address the problem of low RV insertion rate at the input/output pins of logic cells. The vias, called via1, located above the pins are used to connect two wire segments normally on M1 and M2 layers, respectively. Having RVs for via1s is critical to achieving a higher manufacturing yield of an integrated circuit designed with an advanced process technology. Our tool consists of a double-via (DV) aware multilevel router that exploits the via1 doubling possibilities provided to the cells in a conventional as well as a DV-driven cell library. A DV-driven library contains cells with sufficient M1 area for each pin to hold two via1s. Our router determines the locations of redundant via1s above I/O pins whereas our post-routing insertion software determines the positions of RVs other than those specified by the router. The input to the router is a placement design described in DEF and a cell library specified in LEF. Special software is also developed to generate statistics about RV insertion rate, to find out RV candidates around pins for a conventional cell library, and to produce a final DEF with RVs actually installed at a design. The results of insertion can be pictorially observed using any commercial tool that can import a DEF file. Preliminary results show that our approach using a DV-driven library can on average raise via1 doubling rate by 34%, raise total via doubling rate by 11%, reduce the total number of vias by 8%, and reduce the total number of via1s by 22%. This is achieved with an increase of wire length by 3.7% but without perceivable delay increase and virtually no area penalty.

Contact:
Rung-Bin Lin (csrlin@cs.yzu.edu.tw)