We present a tool framework tailored to safe and efficient design entry and refinement of parallelized embedded Systems-on-Chip. Features needed by future commercial design tools are prototypical implemented, such as scripted design entry and edit, transparent HW/SW partitioning, editable graphical design visualization, and multi-chip designs. Compatibility is given to commercial FPGA design suites, such as Xilinx EDK as well as to formal system descriptions represented by Models of Computation.