Because of Shannon’s law the complexity for electronic design grows twice as fast as the chip complexity and chip performance. The productivity improvement of design engineers due to training and improved libraries are insufficient to cope with this problem. In order to achieve the order-of-magnitude productivity improvement of design engineers, it is necessary to move design iterations to higher levels of abstraction, integrate the design flow, and optimize the organizational process for design. Requirements have to become executable, in order to reduce the large error probability in this area. Examples of an integrated design flow will be demonstrated, that include Simulation of the mission or operational level, performance simulation of executable specifications, functional level simulation, code generation, software performance estimation and validation in overall performance model and hardware-in-the-loop simulation. Additionally process simulations of Design and quality-in-design processes, Organizational processes and production processes will be demonstrated. The demonstrations will be done with the tool MLDesigner, tool extensions and couplings with other tools.

Contact:
Prof. Dr. Horst Salzwedel (horst.salzwedel@tu-ilmenau.de)