Parallel multipliers are utilized in high-performance systems because of their high computation speed. The reduction-tree, which is a multi-operand adder in the core of the multiplier, exhibits arithmetic equivalencies due to commutativity and associativity properties of addition. Therefore, when designing the reduction-tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this demonstration, a method will be presented for generation of power-efficient parallel multipliers in such a way that its partial products are connected to minimize activity. The reduction-tree is designed progressively. At each stage of the reduction tree, a simulated annealing optimizer uses power cost numbers from a specially implemented probabilistic gate-level power estimator and selects a power-efficient solution. The influence of optimization will be demonstrated on full-adder based partial product reduction trees. VHDL simulation using ModelSim shows a significant reduction in the overall number of transitions. The spatiotemporal correlations between input operands of the multiplier can also be considered in this method. The optimization algorithm, power estimator and VHDLgenerator are implemented in C++.

Contact:
Saeeid Tahmasbi Oskuii (saeeid@iet.ntnu.no)