We are presenting a tool for hierarchical testing and debugging of systems. It provides testing capabilities at the design specification level before the actual design of the hardware to eliminate many redesign iterations that are necessary for making circuits testable. The package consists of several built-in methods for fault recovery. It includes a library of Timed Automata model of communications in various abstraction levels for automatic fault simulation and localization, facilitating multi-level debugging, and mapping TL faults to stuck-at gate level faults.