This demonstration provides a test tool set that is based on PLI and VPI interfaces of the Verilog HDL. The tool set includes code coverage analysis, and utilities for evaluation of test and testability methods. The test components are mechanisms for fault injection, fault simulation, test generation, DFT, BIST evaluation and test-point insertion. A dynamic power estimation tool has also been included in the package for measuring test power in order to cope with low-power testing related problems. Our tool set includes a netlist generation program that converts EDIF-2 format to proper format for our HDL-based test analysis.