We will demonstrate an H.264/AVC main profile video, coded in synthesizable Verilog RTL and strictly following guidelines for IP reuse. Our design is very small at 170K-gate and power efficient due to innovative algorithm and architecture design. It is integrated in a locally-developed AMBA-based multimedia SOC platform, which has successfully demonstrated JPEG and MPEG4 codec in our previous projects.

Contact:
Youn-Long Steve Lin (ylin@cs.nthu.edu.tw)