3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chips (NoCs), which are thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D should be justified with improvements in performance, power or latency. We developed a framework that can support 2D and 3D NoCs system simulation and evaluation. Users can select different design parameters (i.e. buffer size, topology (different number of TSVs for 3D), architecture, routing algorithm, area size and technology). We established a generic scalable pseudo application (GSPA) and included a wide range of state-of-the-art benchmarks to provide the sufficient complex scenarios for NoCs exploration. These test scenarios can also be used for mapping, placement and scheduling research as application models. A Graphic User Interface (GUI) has been built for the framework. Users can observe the system and local behavior while the simulation processing, e.g. the state of the Processing Elements (PE) and buffer (distributed memory) demands for the application traffic scenarios and given constrains. We also created a real 3D communication monitor, which can support users to obtain a straight view of the utilization of each link in the overall 2D and 3D systems. After the simulation, the detailed evaluation report will be generated automatically, which include all the NoCs system configuration information, the overall time demand of the simulation, throughput, distributed memory demands, links utilization, system interconnect power and energy consumption, TSV utilization and so forth. We employed this framework to build a FPGA prototype demonstration, and have shown that the real-time hardware emulation results and the framework simulation results are consistent.