One major issue in future MPSoC designs is the combined hardware and software development, often referred to HW/SW co-design. Here, both hardware and software are developed in parallel manner, imposing new design challenges to the system architects. E.g. software development for a dedicated processor core, which is still under development, can only start when at least the processor's instruction set is defined and mostly a C compiler is available. Unfortunately such dependencies do not allow parallel design of both soft- and hardware. Additionally, evaluation in terms of fulfilling the requirements of the complete MPSoC can only be performed, when each hardware block and software code is finally developed. To cope with this issue during MPSoC design we have proposed a higher abstraction level, where an abstract processor simulator called Virtual Processing Unit (VPU) is utilized. Main focus at this abstraction level is to identify the topology and required elements of the MPSoC platform. The VPU allows system architects to evaluate their design decisions during system development even before the underlying hardware or software implementation is finally available. Thus, evaluation can take place at all times, that the addressed HW and SW implementation of the complete system achieves the necessary requirements. Therefore, false design decisions, over-designed systems or systems that do not achieve the necessary requirements can be prevented right from the start of the design cycle. Additionally the proposed technology and workbench shown in the demonstration allows a seamless refinement of the software and hardware to well known technologies like instruction accurate and cycle accurate ESL system simulations. The demonstration will highlight the technology of the proposed workbench and technology on top of a case study from the wireless communication domain, namely the transmit part of the WLAN 802.11a standard.

Contact:
Torsten Kempf (torsten.kempf@iss.rwth-aachen.de)