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CAERT - Compiler Assisted Energy Reduction Techniques for Embedded Processors
Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by post-layout simulation. Secondly, based on the energy model mentioned above, the demonstration shows techniques for reducing the energy consumption by optimally mapping program code, stack frames and data items to the scratch-pad memory (SPM) of the processor memory space.