Logic synthesis of the control path from STGs (VeriSAT tools), interfaced to Petrify (Technical University of Catalonia).

Publications:
A. Madalinski, A. Bystrov, V. Khomenko and A. Yakovlev. Visualisation and resolution of encoding con icts in asynchronous circuit design, IEE Proc. CDT, vol. 150, No.5, Sept. 2003, pp. 285-293 (Special issue of Best papers at DATE2003).

Contact:
Agnes Madalinski (a.a.madalinski@ncl.ac.uk)