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BESST tool kit: VERIMAP

Fri, 10/26/2012 - 15:43 — Andreas Vörg, eda...
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(unregistered) Author(s): 
Danil Sokolov
Julian Murphy
Alex Bystrov
Alex Yakovlev
Download URL: 
http://async.org.uk/besst/
Homepage: 
https://www.rd-access.eu/edatools/system/files/ubooth_submission/2005/Descriptio...

Synthesis of data path blocks with security features (VeriMap tool).

Publications:
D. Sokolov, A. Bystrov, A. Yakovlev, Tools for STG Optimisation in the Direct Mapping of Asynchronous Circuits, Second UK ACM SIGDA Workshop on EDA, Bournemouth, 16-17 Sept. 2002.

Contact:
Danil Sokolov (danil.sokolov@ncl.ac.uk)

Project Information
Project Acronym: 
BESST
Project Homepage: 
http://async.org.uk/besst/
Project Description: 
Behavioural Synthesis of Systems with Heterogeneous Timing:


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