This demo presents the µSpider CAD tool for network on chip design under latency and bandwidth constraints and described the different steps of the associated design flow. We show: 1) how the tool can be used to automatically generate a NoC IP compliant with Xilinx EDK tool and 2) a real case implementation of a video application running on a Virtex2pro FPGA, the architecture includes 2 Mblaze, 1 PPC and our NoC IP.

Contact:
Rachid DAFALI (rachid.dafali@univ-ubs.fr)